- The AI-Native Chip Design Challenge, a €40 million joint effort by SPRIND and NADI, targets the verification and architecture exploration phases of chip design, where two-to-four-year timelines currently bottleneck development.
- The 20-month program funds seven initial teams at €2.6 million each, then cuts to three finalists at €7 million apiece, with technical and commercial coaching included to close the gap between design and manufacturable silicon.
- US export controls now covering EDA software make European chip design self-sufficiency more urgent; this challenge is NADI’s first joint program with SPRIND and addresses a design-layer gap the European Chips Act largely left unresolved.
Germany’s SPRIND and the newly launched Dutch National Agency for Disruptive Innovation (NADI) have pooled €40 million on a single chip design program, the first time the two agencies have funded anything together. The AI-Native Chip Design Challenge targets the verification and architecture exploration phases that currently stretch chip development to two to four years, and the ambition, per SPRIND’s head of challenges Jano Costard, is “several orders of magnitude acceleration” in that process.
How the Money Flows
The program runs for 20 months across two stages. Stage 1, from November 2026 to July 2027, funds seven teams at €2.6 million each to develop AI-driven chip design methodologies. Stage 2 cuts that field to three teams, each receiving €7 million for a full year of development. Teams also get technical and commercial coaching, an acknowledgment that the gap between a working chip design and a manufacturable product is where most academic efforts stall.
NADI only launched this month, backed by €500 million in Dutch government funding. SPRIND has been operating since 2019. Both agencies are modelled on DARPA’s high-risk, high-reward structure: they fund approaches that conventional venture capital avoids because failure probability is high and time horizons are long. The chip challenge fits that profile exactly.
The Verification Bottleneck
Bringing a chip from specification to tape-out currently takes two to four years, driven by the complexity of verifying billions of transistors against hundreds of failure modes. The challenge targets that phase specifically, using AI to generate and evaluate candidate designs faster than human engineers can. The goal is not incremental improvement to existing EDA workflows, it is replacing the core loop.
What Each Country Brings
ASML’s dominance in extreme ultraviolet lithography gives the Netherlands a direct line into the manufacturing process for the world’s most advanced chips. That matters because AI-native chip design that cannot be fabricated at scale stays academic. The Netherlands also hosts imec, whose hardware-software co-optimisation work on AI accelerators gives the program a ready source of fabrication-adjacent expertise.
Germany contributes on the research and industrial side. Its university and Fraunhofer institute network has deep roots in processor architecture and embedded systems, workloads that overlap directly with the efficient inference hardware the challenge is trying to build. Dutch fab-ecosystem proximity paired with German research depth is the structural logic behind the partnership.
Sovereignty as the Subtext
The European Chips Act, first passed in 2022 and updated in June 2026, has mobilised over €52 billion in public and private investment aimed at expanding Europe’s share of global semiconductor production. Fabrication capacity drew most of that attention; the design layer did not. Europe can access ASML’s machines. It has far fewer homegrown teams capable of designing the chips those machines would print.
US export controls now covering chip design software itself make that gap harder to ignore. Building design capability from scratch takes longer than a 20-month program window suggests, and the NADI-SPRIND challenge is one response, not a solution.
As of the September 23 announcement, neither agency has named winning teams, published a target chip specification, or set a prototype delivery date. The next concrete milestone is the November 2026 Stage 1 kickoff.
