- Global AI infrastructure spending is projected to surpass $2 trillion in 2026, with hyperscaler capital expenditure already straining supply chains for HBM memory and advanced packaging.
- TSMC’s CoWoS advanced packaging capacity is sold out through 2026, with Nvidia reportedly securing roughly 60% of total global allocation for its Rubin chips, according to reports, leaving other chipmakers competing for the remainder.
- HBM4, expected in the second half of 2026 with 1.5 TB/s bandwidth per stack, arrives into a shortage market: Micron has forecast HBM supply constraints extending beyond 2026, meaning early procurement agreements with SK Hynix and Micron are now a concrete cost lever, not a planning preference.
Hyperscalers plan to spend hundreds of billions on AI infrastructure in 2026, and the supply chain is already struggling to keep up. The bottlenecks are not theoretical. HBM memory is sold out, advanced packaging capacity is gone, and rack power densities are climbing faster than most facilities were built to handle.
Next-Gen AI Accelerators Reshape Compute
Nvidia‘s Blackwell architecture is the current benchmark. Built on a custom TSMC 4NP process with 208 billion transistors, Blackwell GPUs feature 5th Generation Tensor Cores supporting FP4 precision. The Blackwell Ultra variant, the company claims, pushes performance up to 50 times higher for agentic AI applications.
AMD is closing ground with its Instinct MI300X and MI350 GPUs, picking up customers including MicrosoftOracle, Meta and OpenAI on the strength of competitive pricing and the open-source ROCm software platform. AMD’s share of the AI accelerator market remains well below Nvidia’s, though some estimates put its near-term ceiling around 7%. The AI processor segment overall is estimated to account for roughly 47% of the $76 billion AI hardware market in 2026.
HBM Innovation Drives Memory Throughput
The near-term HBM story is shortage, not growth. Micron Technology has forecast memory supply constraints extending beyond 2026, with HBM pricing expected to rise, which could push up the cost of AI-capable servers materially.
SK Hynix currently leads the HBM market, built largely on its early qualification of HBM3E with Nvidia. HBM4, expected to reach mainstream adoption in the second half of 2026, is designed to push bandwidth to 1.5 terabytes per second per stack. For infrastructure teams, the practical consequence is straightforward: budget for higher memory costs now, or risk supply disruptions later. The scarcity puts a premium on early procurement relationships with SK Hynix and Micron.
Advanced Packaging Breaks Bottlenecks
The packaging constraint may be the tightest single chokepoint in the 2026 AI supply chain. TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) technology bonds multiple silicon dies into a single high-performance unit, the process that makes chips like Blackwell possible. TSMC is expanding CoWoS capacity from roughly 35,000 wafers per month in late 2024 to a projected 130,000 by end of 2026, but capacity is already sold out through the year.
Nvidia has reportedly secured roughly 60% of total global CoWoS demand for 2026, primarily for its next-generation Rubin AI chips, according to reports. That leaves Broadcom, Google (for its Tensor Processing Units) and others competing for the remainder. The pressure is pushing TSMC to outsource some work to ASE and Amkor; ASE has projected its advanced packaging sales will double in 2026. For chipmakers outside Nvidia, securing long-term foundry agreements is less a strategic option than a survival requirement. This dynamic is also visible in the race to develop custom silicon, as covered in our look at the OpenAI and Broadcom Jalapeño chipwhere packaging access is equally central.
Power and Cooling Redefine Data Centers
Rack densities are climbing to 30-40 kW or above, up from a current average of around 16 kW. Air cooling cannot handle that load. Liquid cooling has moved from specialist option to practical necessity, with around 19% of data centre operators having already implemented it and more planning adoption. The metric infrastructure teams are now optimising for is tokens per watt, not just raw compute density.
Microsoft has cut energy overhead through direct liquid cooling in its AI facilities. Global data centre electricity demand is projected to reach unprecedented levels this year, and the power constraint is shaping procurement decisions as directly as GPU availability.
Optical Interconnects Enable Scale
At the scale of modern AI clusters, moving data between chips is as much a constraint as computing it. Electrical interconnects hit bandwidth and energy limits that optical alternatives can sidestep. Silicon photonics, using wavelength-division multiplexing architectures, can enable terabit-scale data movement with meaningfully better energy efficiency. Research from Seoul National University, published in Electronicsfound that replacing electrical interconnects with optical ones in multi-chip machine learning architectures reduced training time, with the paper reporting reductions that varied by interconnect speed and model type.
Companies including Lightmatter are commercialising photonic interconnects and co-packaged optics (CPO). Cisco released a 102.4 Tbps networking chip in February 2026, a data point that illustrates the bandwidth demands now being placed on the transceiver supply chain. For infrastructure teams planning large-scale AI deployments, optical interconnect capability is increasingly a procurement variable alongside GPU count and memory bandwidth.
The five constraints covered here, compute, memory, packaging, power and interconnects, are not independent. A shortage in any one limits what the others can deliver. The HBM and CoWoS situations are acute enough in 2026 that procurement strategy, not just engineering capability, will determine which organisations can actually deploy AI at scale. For more coverage of AI chips and infrastructure, visit our AI Hardware section.
