- Samsung has started partial 2nm production at its Taylor, Texas fab, anchored by a $16.5 billion deal with Tesla for AI5 chips spanning electric vehicles, autonomous driving and AI data centres.
- SK Hynix’s $15 billion manufacturing investment targets HBM4 production in 2026, with bandwidth exceeding 2 terabytes per second and capacities up to 48GB per stack, pushing memory specs well ahead of current HBM3E shipments.
- Japan’s Rapidus is pricing 2nm wafers at ¥3 million to ¥3.5 million each, below TSMC’s current rates, backed by ¥631.5 billion in government subsidies and a technology transfer from IBM’s Albany NanoTech Complex.
Samsung started partial 2nm chip production in Taylor, Texas ahead of schedule, anchored by a $16.5 billion Tesla order, while Japan’s government-backed Rapidus approved its 2nm production budget and is pricing wafers to undercut TSMC. The two moves, arriving in the same quarter, show how quickly the foundry and memory race is tightening outside the US.
Samsung’s 2nm Texas Start
Samsung Electronics reportedly began trial production of 2nm chips at its Taylor, Texas plant in mid-September 2026, moving up its original schedule, with full volume production still expected in the second half of 2027. The ramp is driven by Tesla, whose $16.5 billion semiconductor deal with Samsung covers next-generation AI5 chips for electric vehicles, autonomous driving and AI data centres.
Samsung is also integrating AI at the design and process level. In September 2026 the company announced a partnership with Mistral AI to embed large language models across its semiconductor engineering and manufacturing operations. The collaboration targets on-premises AI models for defect detection and equipment optimisation, keeping sensitive process data in-house while the company works to stabilise yields on advanced memory and logic chips.
SK Hynix’s HBM4 Push
At Hot Chips 2026 in August, SK Hynix laid out its HBM roadmap in detail. HBM3E remains the dominant AI memory product for most of 2026, but SK Hynix confirmed at Hot Chips 2026 that its 12-layer HBM4 is already in mass production, with the 16-layer version now in customer qualification, targeting bandwidth exceeding 2 terabytes per second and stack capacities up to 48GB. For context, HBM3E tops out around 1.15 terabytes per second, so HBM4 is a substantial step, not an incremental one.
The $15 billion investment SK Hynix announced in February 2026 is funding the Through-Silicon Via stacking lines and CoWoS-aligned packaging capacity needed to supply NVIDIA, AMD and Intel at scale. Further out, the company is developing hybrid bonding for HBM5, expected around 2029 to 2030, to handle the power and thermal demands of future high-density stacks. On HBM supply investment more broadly, Micron has made parallel commitments running to similar scale.
Rapidus Targets 2nm by Late 2027
Rapidus is targeting 2nm mass production by the second half of fiscal 2027, using IBM’s Gate-All-Around nanosheet process. More than 150 Rapidus engineers trained at IBM’s Albany NanoTech Complex to get there. The company secured ¥267.6 billion (approximately $1.7 billion) in combined government and private funding in February 2026, with a further ¥631.5 billion (around $4 billion) in government subsidies approved this year through Japan’s New Energy and Industrial Technology Development Organization.
The pricing strategy is direct: Rapidus is targeting wafer fabrication costs of ¥3 million to ¥3.5 million (roughly $18,460 to $21,540) per wafer, at or below TSMC’s current 2nm rates. In April 2026, NEDO approved Rapidus’s fiscal 2026 budget covering 2nm integration technologies, short-turnaround manufacturing and chiplet/package design. The company has also begun developing a 1.4nm process, with fab construction planned for 2027 and mass production targeted around 2029.
South Korea’s $950 Billion Semiconductor Push
At the San Francisco AI Summit on July 24, 2026, South Korea announced semiconductor cooperation worth a combined $950 billion with global technology firms. SK Group signed five-year advanced memory supply partnerships with NVIDIA and others; Samsung expanded cooperation with Broadcom across memory, AI chip foundry services and advanced packaging.
The government had already approved an 8.6 trillion won ($5.77 to $6.5 billion) strategy in March 2026 as part of a five-year roadmap through 2028. That plan includes the K-On-Device AI Semiconductor Technology Development Project, which allocates approximately $664 million from 2026 to 2030 to develop 10 on-device AI chips by 2030. A separate $650 billion public-private investment plan running through 2035 combines Samsung and SK Hynix commitments for four new fabs, HBM packaging, next-generation memory and 18.4 gigawatts of AI data centre capacity.
Japan’s ¥370 Trillion Technology Bet
Japan’s broader economic strategy targets ¥370 trillion (approximately $2.3 trillion) in public and private investment by fiscal 2040, with ¥101.6 trillion earmarked specifically for AI and semiconductor spending. The Ministry of Economy, Trade and Industry has backed Noetra, a new company supported by major Japanese industrial firms, with ¥1 trillion to develop physical AI foundation models. The stated goal is 10 million AI-equipped robots deployed across 18 sectors by 2040, with labour shortages cited as the primary driver.
Semiconductors sit at the centre of that plan: without domestic leading-edge fabrication, Japan cannot control the hardware layer beneath its robotics and industrial AI ambitions. Rapidus is the critical piece, and its 2027 mass-production target leaves almost no margin for further delays. Whether the ¥631.5 billion in subsidies is enough to close that gap against TSMC and Samsung’s existing process advantages is the question Japan’s industrial policy now rests on.
